Double data rate (DDR) systems have multiple dual in-line memory modules (DIMMs) directly attached to a memory controller. When the DIMM ranks increase, the maximum operating frequency can decrease due to parallel loading. Current load-reduced (LR) DIMM have data buffers on DIMMs, employing a low-capacitance input buffer and output driver to hide and buffer the dynamic random access memory (DRAM) load from the bus. But the branches on the signal transmit path still limit the bandwidth of the channel.